This application claims benefit of priority to Japanese Patent Application No. 11-181690 filed Jun. 28, 1999, the entire content of which is incorporated by reference herein.
1. Field of the Invention
This invention relates to an NPC(Neutral Point Clamped) inverter control system composed of a direct-current (DC) power source having multiple electric potentials created by a neutral point and multi-level inverter circuits constituted of a plurality of semiconductor devices such as IEGT(Injection Enhanced Gate Transistor) or IGBT (Insulated Gate Bipolar Transistor). More specifically, the invention relates to an NPC inverter control system which ensures safe operation of the semiconductor devices constituting the multi-level inverter circuits and reduce switching loss of the semiconductor devices.
2. Description of the Background
FIG. 1 shows one example of this kind of a conventional NPC inverter control system.
FIG. 1 gives one constituent example showing only one phase of a three-level inverter apparatus as a representative example.
In FIG. 1, the three-level inverter apparatus is composed of a DC power source and three three-level inverter circuits (only one is shown) as multi-level inverter circuits.
The DC power source forms a neutral point corresponding to a junction of two DC powers 1a and 1b serially connected with one another, a positive electrode and a negative electrode.
One of the three-level inverter circuits, controlling a U-phase, is composed of four semiconductor devices US1, US2, US3 and US4 with gate controllers, such as IEGT(Injection Enhanced Gate Transistor), and two diodes UD1 and UD2. The semiconductor devices US1, US2, US3 and US4, and the diodes UD1 and UD2 are connected as shown in FIG. 1 and invert the DC power to an alternating current (AC) power and supply the AC power to a load, such as a motor (not shown in FIG. 1).
An explanation of the operation of the three-level inverter circuit is omitted in this description because of its well-known nature.
Conventional snubber circuits are provided to protect the four semiconductor devices US1, US2, US3 and US4 and two diodes UD1 and UD2 constituting one of the three-level inverter circuits from an excess voltage.
With the increase of a capacity of the three-level inverter circuit, either charge and discharge type of snubber circuits S11a, S11b, S12a and S12b respectively connected to the semiconductor devices US1, US2, US3 and US4 shown in a portion A of FIG. 1, or clamp type of snubber circuits S21a, S21b, S22a and S22b shown in a portion B of FIG. 1 are used.
In recent years, with the advance of a voltage driven type of a semiconductor device having a large capacity, a large current can now be turned on and off.
Non-saturatable reactors 2a and 2b for reducing a rate of a rise of current dl/dt at a time of turning on, are usually provided between the three-level inverter circuit, and the respective positive and negative electrodes of the DC power source in order to prevent the semiconductor devices US1, US2, US3 and US4 from being destroyed by a sudden rise of a current. The sudden rise of a current especially occurs when a free wheel diode recovers in the opposite way because of the switching on of a semiconductor device positioned at the opposite side of the diode under a condition that a reverse recovery current is flowing into the free wheel diode.
However, using the above-mentioned snubber circuits and the non-saturatable reactors 2a and 2b suffer from the drawback that they become large and costly with the increase of a capacity and a voltage of the three-level inverter circuit.
On the other hand, in recent years, with the advance of a voltage driven type of a semiconductor device, a high voltage, large current can be turned on and off at high speed, for example, a high voltage and large capacity inverter circuit controlling several thousands of DC volts is put to practical use as a multi-level inverter circuit.
However, as described above, it is desired to improve the multi-level inverter circuit, because of the problems of a cost and reliability resulting from the snubber circuits and the non-saturatable reactors 2a and 2b, which include many components rendering an NPC inverter control system large in size.
Accordingly, one object of this invention is to provide an NPC inverter control system which reduces a rate of a rise of current dl/dt of a current flowing into a semiconductor device constituting a multi-level inverter circuit and improve miniaturization, a cost and reliability.
In accordance with the above intention, the present invention provides an NPC inverter control system, including a DC power source having a neutral point located at a junction between a pair of capacitors which are serially connected with a positive electrode and a negative electrode. A multi-level inverter circuit having a plurality of semiconductor devices is coupled to the DC power source and configured to invert the DC power source to an AC power and to supply the AC power to a load. The control system further includes a plurality of saturatable reactors configured to join the positive and negative electrodes of the DC power source to the multi-level inverter circuit.